Difference between revisions of "Logic Model Theory"
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* The Verification of a Logic Model is to verify the attribute of the model based on ARGS[LM]. It does not depend on the State. | * The Verification of a Logic Model is to verify the attribute of the model based on ARGS[LM]. It does not depend on the State. | ||
Verification[SC, ARGS] => some SC is determined | Verification[SC, ARGS] => some SC is determined | ||
* The verification counterpart | * The verification counterpart of LM, VLM, which is also a logic model: | ||
* The relation between LM and VML: | * The relation between LM and VML: | ||
Context[VLM]: share with LM (?) | Context[VLM]: share with LM (?) |
Revision as of 09:16, 29 August 2021
A logic Model entity :
LM
The list of 7 arguments of a logic model:
ARGS[LM]
the arguments are separated into 2 parts
Abstract[LM] Concrete[LM]
- the Abstract[LM] base/frame the Concrete[LM]
- The Implementation of a Logic Model is based on Concrete[IM]. When implementing, the input starts to be actually transformed into output by the specified process (deterministic or non? or both?).
- The actual input, actual process, actual output is
State[LM]
- The Evaluation of a Logic Model is to compare the output and the Success Criteria to check whether the SC is finished.
Evaluation[SC,State] => the SC[LM] is determined
- The Verification of a Logic Model is to verify the attribute of the model based on ARGS[LM]. It does not depend on the State.
Verification[SC, ARGS] => some SC is determined
- The verification counterpart of LM, VLM, which is also a logic model:
- The relation between LM and VML:
Context[VLM]: share with LM (?) Goal[VLM]: Verify LM Success Criteria[VLM]: Correctness, Speed, Completeness of Verification Ouput[VLM]: Verification results, predicting which conditions will meet in which conditions and why (additionally, the process information helps itself to optimize) Process[VLM]: Workflows (need examples) Input[VLM]: The Logic Model which is in the accepted domain. Boundary condition: ?